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3D DRAM research
  • Since the design rule (D/R) of 10 nm is expected to be the scaling limit in two-dimensional (2D) planar DRAM structure, a breakthrough is necessary to overcome the physical limit to improve memory performance continuously. At the D/R of 10 nm 2D DRAM, the acceptable electrode and dielectric thin film thickness should be 3 nm or less, which is an extremely challeging target to meet both from the material and process points of view.
  • Three-dimensional (3D) stacked DRAM could be a feasible alternative to achieve increased density without relying on device scaling. Therefore, two types of structure (vertically stacked structure_1T-1C vertically connected / horizontally staked structure_1T-1C horizontally connected, see figures below) were suggested by our research group. Both structures require 1) a manufacturing process of 3D stacked cell, 2) Improvement of unit device (Capacitor, Transistor, interconnect) characteristics.